Project

AI compiler

AI compiler translates neural network into low level device code, e.g., CUDA. It plays a critical role to ensure the efficient scaling of neural network.

In the past, we developed a series of compiler techniques to advocate the tile-based abstraction on canonical deep learning compilation on SIMT based AI hardware (e.g., GPU). This includes Rammer (Ma et al., 2020), Roller (Zhu et al., 2022), Welder (Shi et al., 2023), and Cocktailer (Zhang et al., 2023). These techniques were covered in an MSR Research blog. And the tile abstraction is now well recognized in the systems community.

In addition, we correctly envisioned the importance of taking model sparsity into account in compiler techniques, and developed the first sparsity-aware compilers, SparTA (Zheng et al., 2022), PIT (Zheng et al., 2023), and nmSPARSE (Lin et al., 2023), and compilers for low-bit neural models, e.g., Ladder (Wang et al., 2024). They are all successfully unified under the tile abstraction.

Our next focus is compiler techniques for AI hardware with new architecture. For example, the more recent GPUs comes with heterogeneous hardware units, including tensor core, CUDA core, and Tensor Memory Accelerator (TMA). This introduces system opportunities that design new mechanisms that enables sophisticated compute schedule, e.g., pipelining, for extreme performance (Cheng et al., 2025). Another new hardware trend is the distributed memory architecture (i.e., non SIMT) (He et al., 2025). Meanwhile, the programming interface of neural network is an important topic related to compiler techniques. We will continue to investigate in new programming models like tile-lang (Wang et al., 2026) and FractalTensor (Liu et al., 2024).

Interestingly, we observe that compiler techniques are also useful in distributed deep learning training and automated machine learning. Based on the observation, we developed nnScaler (Lin et al., 2024), a flexible and efficient distributed training framework with a checker (Lu et al., 2025), and NNI, an AutoML toolkit (Zhang et al., 2020).

References

2026

  1. TileLang: Bridge Programmability and Performance in Modern Neural Kernels
    Lei Wang, and
    ICLR 2026.

2025

  1. PipeThreader: Software-Defined Pipelining for Efficient DNN Execution
    Yu Cheng, and
    OSDI 2025.
  2. WaferLLM: A Wafer-Scale LLM Inference System
    Congjie He, and
  3. TrainVerify: Equivalence-Based Verification for Distributed LLM Training
    Yunchi Lu, and
    SOSP 2025. ArXiv version.

2024

  1. Ladder: Enabling Efficient Low-Precision Deep Learning Computing through Hardware-aware Tensor Transformation
    Lei Wang, and
    OSDI 2024.
  2. Uncovering Nested Data Parallelism and Data Reuse in DNN Computation with FractalTensor
    Siran Liu, and
    SOSP 2024.
  3. nnScaler: Constraint-Guided Parallelization Plan Generation for Deep Learning Training
    Zhiqi Lin, and
    OSDI 2024.

2023

  1. Welder: Scheduling Deep Learning Memory Access via Tile-graph
    Yining Shi, and
    OSDI 2023.
  2. Cocktailer: Analyzing and Optimizing Dynamic Control Flow in Deep Learning
    Chen Zhang, and
    OSDI 2023.
  3. PIT: Optimization of Dynamic Sparse Deep Learning Models via Permutation Invariant Transformation
    Ningxin Zheng, and
    SOSP 2023.
  4. MLSys
    Efficient GPU Kernels for N:M-Sparse Weights in Deep Learning
    Bin Lin, and
    MLSys 2023.

2022

  1. ROLLER: Fast and Efficient Tensor Compilation for Deep Learning
    Hongyu Zhu, and
    OSDI 2022.
  2. SparTA: Deep-Learning Model Sparsity via Tensor-with-Sparsity-Attribute
    Ningxin Zheng, and
    OSDI 2022.

2020

  1. Rammer: Enabling Holistic Deep Learning Compiler Optimizations with rTasks
    Lingxiao Ma, and
    OSDI 2020.
  2. Retiarii: A Deep Learning Exploratory-Training Framework
    Quanlu Zhang, and
    OSDI 2020.

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